次領域一

前瞻矽基元件與材料(Emerging Si-Based Devices and Materials):以矽基(Si-Based) CMOS、快閃記憶體的核心技術為主軸。相關研究議題如下:

  • (A) 低漏電、低功率/電壓矽基元件技術及scaling
  • (B) 以Si-Substrate為主體的異質整合(Heterogeneous Integration),開發20 nm以下的Ge-Channel及III-V元件技術,提供未來CMOS元件未能持續scaling後的解決方案
  • (C) 以現有SONOS快閃記憶體研究成果,發展奈米晶粒(Nano-Crystal)、分子式(Molecule)奈米快閃記憶體、Resistive RAM等元件技術
  • (D) 非典型元件結構(Non-Classical CMOS),在既有的鰭狀電晶體(FinFET)、多閘極電晶體(MuGFET)基礎下,研究環繞式閘極電晶體、奈米線電晶體、3D電晶體與Flash Memory等非典型元件結構、製程技術、微縮與性能極限,元件物理、載子傳輸、原子級模擬分析、及可靠度等的分析<

Sub-Project I

【Emerging Si-Based Devices and Materials】 combines NCTU’s Nanoelectronics Technology core team and NTHU’s Nanotechnology and Si-Based Devices and Materials core team, focusing on Si-Based CMOS and Non-Volatile Memory. Major research tasks and expected results are described below:

  • (A) Low-voltage, low-leakage/power Si-based device technology and scaling: Due to the small energy bandgap, III-V material-based tunneling field-effect transistors can operate at a lower supply voltage (VDS < 0.25 V) for future ultralow-power consumption logic applications. The novel architecture device can achieve larger tunneling current、lower leakage current with SS < 60 mV/dec. Moreover to reduce impact of parasitic resistance on the degradation of device performance, novel materials and process technologies will be developed to achieve the 2016 requirements projected by the 2009 ITRS, i.e. Schottky barrier height<0.3 eV and contact resistivity<2 -m2.
  • (B) Si-Substrate Based Heterogeneous Integration: The sub-program will develop Ge-channel and III-V channel devices for 20 nm node and beyond logic applications. To achieve high hole mobility, the QWFET will use pure Ge or SiGe as channel materials. The heterostructures for the QWFET system will include GaAs/Ge/GaAs or GaAs/Si1-xGex/GaAs integrated on Si substrate with composite SiGe/InxAl1-xAs metamorphic buffers. Moreover, a compound semiconductor-based p-channel QWFETs structure on InP substrate using high indium content InxGa1-xAs as channel material can also be fabricated. For the mobility enhancement, materials-induced bi-axial strain or uni-axial strain such as using lattice-mismatched source/drain stressor will be incorporated in the transistor-structure. To achieve low metal/Ge contact resistance, Schottky barrier height modulation technologies including surface engineering and metallization technologies will be developed. Physical mechanisms of the Fermi-level pinning will also be researched. The final target is Schottky barrier height<0.3 eV and contact resistivity<2 -m2. For III-V high electron mobility QWFETs, the evaluation of < 40-nm InAs-channel QWFETs for logic applications fabricated with novel structure and advanced process technology will be performed. The development of non-planar, multi-gate MOS-QWFET will also be carried out to improve the scalability of the device with better gate control of the channel for low power logic applications.
  • (C) Emerging Non-volatile Semiconductor Memory Research: Non-volatile semiconductor memory (NVSM) has been a key component in the current information technology (IT) product chain. Its penetration ratio in IT products has already exceeded 90%. However, as the current floating-gate flash memory based NVSM technology is approaching its fundamental physical limitations of 15nm, there is increasing concern about its scalability into a tera-bit era beyond a two-dimensional memory architecture. Various new technologies for next-generation NVSM have been proposed, for example, magneto-resistive memory (MRAM), phase change memory (PRAM), resistive switching memory (RRAM) and charge trapping flash memory (CTF). Among them, CTF and RRAM are considered to be most promising for the future 3D memory array. In this project, we will combine research resources in university and industry to focus on these two technologies, to explore quantum physics-based innovative cell structures and to develop a 3D memory array for tera-bit storage.
  • (D) Non-Classical CMOS: Carbon nanotube (CNT) has attracted much attention because of its excellent electrical, thermal, mechanical and chemical properties. The application of discrete single-walled CNT field effect transistor (SWNT FET) is a long term target. In medium and short terms, using large amount of CNTs to minimize the device deviation, i.e., the CNT network thin-film transistor (CNTN TFT) is more feasible. It is known that the conductivity of the CNTN can be modeled by the percolation theory. Using the percolation theory to design device may obtain high performance CNTN TFTs. We will develop low temperature process CNTN TFTs process on flexible substrate and evaluate the effects of curvature on device performance, transport mechanism, and reliability. Simultaneously, using the percolation theory may obtain ultra-thin CNTN conducting film. Failure mechanism and reliability physics of the CNTN conducting film will be investigated. We will also conduct a comprehensive assessment of Ge and III-V channel based logic circuits and memories (SRAM) using emerging device structures such as Ultra-Thin-Body (UTB) and FinFET devices. Leakage-Delay properties of Ge and III-V UTB/FinFET logic circuits will be comprehensively analyzed including static logic, dynamic logic, latches, and the impact of temperature on the leakage/performance, etc. The stability and performance of Ge and III-V UTB/FinFET SRAMs will be investigated including Read Static Noise Margin, Write Static Noise Margin, Read Access time, Time to Write, cell leakage and intrinsic process variation induced variability. The impact of surface orientation on the stability, performance and variability of Ge and III-V FinFET logic circuits and SRAM cells will also be examined. Our investigation that employs atomistic mixed device/circuit simulations will provide an in-depth understanding of the advantages, constraints, trade-off and merits of Ge and III-V channel UTB/FinFET devices for future logic and memory applications.<

次領域二

新世代奈米材料及元件(Nanostructure Based Meta-Materials and Devices):利用奈米結構,將電子、光子、聲子、電漿子結合,付予半導體材料新的性質與功能。帶來新元件及應用。重點在:

  • (A) 奈米結構的傳輸及磁、光等性質
  • (B) 奈米結構的群體效應(Collective Behavior)
  • (C) 次奈米結構的磁光及機械性質
  • (D) 兆赫波(Tera Hertz)奈材元件,包括發射源、偵測器等
  • (E) 致冷晶片、熱電元件及電漿子元件

Sub-Project II

【Nanostructure-based Meta-Materials and Devices】 explores new possibilities and functionalities of next-generation devices based on semiconductor nanostructures and meta-materials utilizing interactions of electrons, photons, phonons and plasmons. The emphasis will be the following:

  • (A) Semiconductor nano and quantum structures --- their growth and fundamental magneto-optical and electrical-optical properties: We have two molecular beam epitaxial systems, which we have used to grow high quality quantum dots, quantum wires, quantum rings and etc.. Under the support of the previous 5y50B project, we have set up a low temperature, high magnetic system, which is capable of doing PL, Micro-PL, microwave, ellipsometry, SNOM measurements. Most of the features were designed and made by ourselves with some of them unique and best in the world. We will use this system to study the most fundamental physical properties of single quantum structures. We expect the results will shed light on the fundamental problems of nanoscience we face today.
  • (B) Theoretical study of sub-nano structures and atomic scale calculations: Targeting the application of atomic-scale spintronic devices, we will perform quantum simulations of atomic spins on surfaces from first principles. This kind of surface-engineered atomic spins have been fabricated by IBM Researchers during 2005~2007. Such spin systems received wide news coverage because its advance and revolution. Such accomplishments were reported by NBC news, Wall Street Journal, etc. On the other hand, the prototypes of computation bits composed of nanoscale surface spins have been fabricated and were published to Science. The summary above implies that surface-engineered atomic spins will eventually lead to atomic-scale spintronic devices. There are two important physical quantities for surface-engineered atomic spins, spin coupling and single-spin anisotropy. The state-of-the-art Density Functional Theory in the Full-potential Linearized Augmented Plane Wave basis will be used to study the magnetic properties of such novel systems. We will try to change coupling strength by using different magnetic adatoms and geometries. We expect to find one or more suitable atoms and geometries and plan to calculate their spin coupling and other magnetic properties. We will calculate the spin couplings and other electronic properties of those trial systems. We will also calculate the spin anisotropy of atoms and clusters, including two- and three-dimensional construction on surfaces. The effects of different valence orbitals of different atoms on spin anisotropy will also be studied. Besides spin and magnetism, one needs to know the force to move an atom when constructing clusters of atoms, including parallel and perpendicular. We will understand more about the constructing mechanism of atomic clusters, which help avoid multiple experimental trials in fabricating desired spintronic devices.
  • (C) era Hertz sourses, detectors and their fundamental principles: Tera Hertz devices have many applications but it is a big challenge to realize them. They are between photonic devices and electronic devices. The frequency of operation is above the highest frequency obtainable by today’s electronic devices. The wavelength of tera hertz radiation is however longer than those of today’s light emitting devices. In the past, the tera hertz radiation is usually generated either by several stage frequency doublers or by using ultra short laser pulses. The power generated is usually low and they are difficult to use. In this task, we plan to use the existing semiconductor technology to generate tera hertz radiation. Recent reports have shown that short channel PHEMTs are capable of generating tera hertz wave due to the 2-D electron gas plasma wave. Our recent results indicates such radiation is probably due to hot electron-phonon effect and the radiation has a very high power even at room temperature. We are currently designing devices which are able to combine several Tera Hertz sources together to generate even higher power.
  • (D) Thermal electrical devices and cooling chips: To use semiconductor devices to convert heat and electricity is very attractive but challenging subject. Using special semiconductor nanostructure, one maybe able to control the electron transport and the phonon transport separately. In this way, efficient thermal-electric conversion can be achieved. We currently have a joint research program with ITRI trying to use the nonequilibrium electron and phonon distributions to enhance the thermal electric effect. We are also developing a cooling chip using light emission from heterostructures. We plan not only to understand the physics under these effects but also to develop this technology so that we can use them together with other semiconductor devices.
  • (E) Quantum dot electro-dynamics, single photon sources and spintronics: In the area of quantum dots physics and devices, we shall carry out three tasks. (1) QDs dynamics: using time-resolved photoluminescence measurement to study the QDs size effect and temperature dependence in carrier relaxation; building up the state and carrier transition model in QDs. (2) Single photon source and entangled photon pairs: using the exciton and biexciton in single QDs to generate entangled photon pairs; to control the fine structure splitting between exciton and biexciton by electric field to investigate its physics origin and to fabricate the devices emitting polarization entangled photon pairs. (3) photon-exciton polariton: using MBE and processing technique to fabricate 3-D optically confined micro-pillar cavity and to study the photon and exciton interaction, particularly the spin dynamics of polariton formed by the strong-coupling. In the direction of spintronics, we focus on the spin-dependent physics of 2-D non-magnetic semiconductor. There are two main approaches. (1) spin interference separation in 2-D electron gases: with the spin-orbital interaction, spin-up and spin-down electrons separate when they pass through a metal-gated grating. The Kerr microscopy method will be used to observe the non-magnetic Stern-Gerlach experiment. (2) Lateral 2-D p-n diode: using special processing technique to electrically induce 2-D electron and hole gases to form a 2-D lateral p-n junction; to study the 2-D spin Hall effect by measuring the dependence between the current direction and emission polarization. For the growth of nanostructure, apart from the conventional self-assembled nanostructures, we shall also grow the ultra-thin metal file to investigate the 1-D and 2-D quantum confinement effect in metal.

次領域三

兆赫波電路與系統(Tera Hz Circuits and Systems:研發矽製程在Tera Hz 系統之應用。建構Tera Hz 核心元件及電路之自製設計能力,與相闢的微機電及封裝技術。建立Tera Hz 信號頻譜之量測能力。主要方向為:

  • (A) Tera Hz CMOS 信號源設計
  • (B) Tera Hertz CMOS 射頻照影偵測器陣列系統晶片
  • (C) 應用微機電之兆赫波導結構設計
  • (D) Tera Hz量測技術
  • (E) Tera Hz 醫學影像系統之建構與技術發展。

Sub-Project III

【Tera Hz Circuits and Systems】 Tera Hz radiation is electromagnetic wave with frequencies between 300 GHz and 3 Tera Hz. We will develop design and simulation techniques for silicon-based Tera Hz circuits. We will use advanced IC technologies incorporating new high-speed devices to implement Tera Hz circuits and develop 3D packaging carriers to assemble Tera Hz systems. We will develop Tera Hz measurement techniques to characterize Tera Hz circuits and systems. We will seek research collaborations with world-leading Tera Hz research groups (e.g. UCLA) to improve our design and implementation capabilities for Tera Hz circuits and systems.

  • (A) Tera Hz Circuit Design and Simulation Technology: This part includes the design of THz source and THz array receiver circuit designs. The THz source circuit includes the RF oscillator, phase locked loop, corresponding phase shifter and the LO signal distribution networks. The major goal of the design is to increase fundamental oscillation frequency and the output power of an oscillator. We can distribute signals to many antennas by using phase shifter and LO signal distribution networks. Moreover, we can raise the equivalent output power of THz source by using phased array. The main objective of THz array receiver research is to increase conversion gain, dynamic range and improve the detection methods of THz RF array. There are two key circuits in the THz array receiver: low noise amplifier and RF mixer, and they determine the highest operating frequency of the system. In the low noise amplifier, we optimize the noise factor considering impedance matching, and improve the performance of LNA in THz. As for THz RF mixer, we will raise conversion gain, reduce noise figure and improve linearity. All circuits will be fabricated in a 40nm CMOS process. We will analyze, design circuits and layouts. Then, we will do the whole chip system simulations include electromagnetic simulations. Finally, the circuits will be fabricated through foundry services. The chips will be packaged and measured to verify their performance.
  • (B) Tera Hz Packaging Technologies: In this subtask, a high performance THz antenna system is aimed to be developed by adapting the design concept of 3D horn structure and antenna array with a silicon-based multi-chip module (MCM) packaging technique for enhancing the signal transceiving capability in a THz imaging system. Research efforts including THz field analysis, signal coupling design of transmission line (TML) to antenna array, the development of silicon micromachining with chip stacking technique have been outlined and will be deployed for realizing the design and fabrication of the proposed antenna. Via the flip-chip chip assembly on a single package scheme to reduce signal loss within chips and the horn structure for better bandwidth, directivity, and gain, it can be expected that the antenna gain with the design can be boosted with more than 10dB enhancement in comparison with the conventional THz antenna.
  • (C) Terahertz Measurement Technologies: We focus on three major technologies, (1) THz spectral analysis -calibration and measurement, (2) THz absolute power -calibration and measurement, and the last, (3) THz noise calibration and measurement. Current commercial RF measurement systems can only measure circuits up to 110GHz accurately. From 110GHz to 220GHz, commercially available measurement technologies are incomplete. As for signals over 220GHz, there is no unanimous calibration standards. Therefore, the calibrations and measurement technologies in THz band have decisive influences on the measurement quality of THz circuits.
  • (D) Tera Hz Image System: The project is to develop miniaturized THz imaging system for medical applications. As THz spectrum is beyond the scope of most of the instrument vendors, it is essential to build up in-house facilities for system and device characterization. On the other hand, the key components including electrical and optical devices will be developed to replace commercial parts. The action items including the construction of dental imaging system, and define system specifications for component development. Both the reflection and transmission type optical system will be investigated for feasibilities study. The ultimate goal is to build up an experimental prototype which integrates the in-house developed signal source and detector.

次領域四

綠能運算與儲存IC (Green Computing and Storage IC):探討適合於下世代可攜式行動裝置的新應用,研發關鍵的系統架構和電路設計技術,以達成微瓦級的低功耗系統實現方案。同時持續研發整合智慧感測與訊號處理的關鍵技術輿操作於次臨界電壓的儲存記憶體(如暫存器及靜態隨機存取記憶體),並搭配創新的無石英(Crystal-less)通訊系統解決方案,以供計算、通訊、以及多媒體、影像、生醫與知覺系統之應用

Sub-Project IV

【 Green Computing and Storage IC】 explores next-generation portable devices and applications with a focus on developing key system architecture and circuit design techniques for ultra-low-power μW system solutions. We will also continue developing subthreshold memory (such as register file, FIFO, and SRAM) for ultra-low-voltage/power storage and crystal-less oscillator for communication IC to provide solutions and platforms for ultra-low-power computation, communication, multimedia, imaging, bio-medical and sensory system applications.

  • (A) Sensor and Read-Out Circuits: Smart sensing devices are the key elements for better life and better environment since multi-physics signals (like voice, light, heat, strength, electricity, chemical reaction, …etc) are demanded to construct future intelligent electronics systems. Very often low-power analog to digital converters (ADC’s) are necessary to convert these sensed signals to digital domains for feature extraction and storage. In this topic, we’ll first explore new read-out circuits to sense out resistance, capacitance, and voltage variations. Furthermore we’ll study the integration of these read-out circuits and CMOS-MEMS sensors to come out smart sensing modules for portable applications.
  • (B) Low-Power System Architecture and Circuits: For ultra-low power designs, we’ll explore design techniques for those building blocks used in Body Channel Communications (BCC), including modulation/de-modulation, error control coding, and front-end driving, security with resistance to power attack. Moreover, we’ll continue the research on crystal-less communication system derived from 1st phase and study the feasibility of crystal-less BCC solution for touch-panel based portable devices. As a result, various applications can be linked to cloud services via internet, covering multimedia and sensed signals. This platform will be served as a demonstrator to evaluate performance indices and provide a channel to better life and better environment.
  • (C) Low Voltage Storage Circuits: As sensing devices become popular, more and more storage spaces are demanded to store large volumes of sensed data. In this topic, we’ll explore some low-power design techniques for solid-state disk (SSD) solutions. Related error control codes to improve flash memory read/write accesses will also be addressed. In addition, low-voltage circuit designs for embedded SRAM will be investigated. As a result, a unique low-power memory hierarchy solution will be developed to meet the requirements of portable applications.
  • (D) Energy Harvesting Circuits: The application scenario for smart sensing modules needs to be very user-friendly, especially about the power supply for long-time usage. Currently some solutions are based on wireless power and energy conversion mechanisms. For continuous monitoring with long period, it is necessary to enhance energy conversion ratio. Thus we’ll explore new energy harvesting solutions which exploit intelligent control schemes. As a result, energy efficiency can be further improved and related smart sensing modules can be applied widely for better life.